CPO Foundry Roadmaps: TSMC, Intel, Samsung, and GlobalFoundries Compared

TSMC, Intel, Samsung, and GlobalFoundries are developing competing Co-Packaged Optics (CPO) roadmaps to address the bandwidth and power constraints of AI data centers. CPO integrates optical connectors directly into the semiconductor package, moving the electrical-to-optical conversion closer to the processor to reduce signal loss and energy consumption compared to traditional pluggable transceivers.

The industry shift toward CPO is driven by the scaling requirements of Large Language Models (LLMs), which demand massive throughput between GPUs and accelerators. According to technical roadmaps from these foundries, the goal is to replace copper traces and traditional optical modules with integrated silicon photonics to sustain the growth of cluster-scale connectivity.

TSMC and the Integration of Silicon Photonics

TSMC is positioning itself as a primary foundry for CPO by leveraging its advanced packaging ecosystem. The company focuses on integrating silicon photonics with its CoWoS (Chip on Wafer on Substrate) technology. By placing the optical engine on the same package as the compute die, TSMC aims to minimize the distance electrical signals must travel, which directly reduces power leakage and latency.

TSMC’s approach relies on a foundry model where it provides the manufacturing infrastructure for fabless designers to implement their own optical IP. This allows chipmakers to customize the number of optical lanes and the specific wavelengths used for data transmission without needing to build their own photonics fabs.

Intel’s Vertical Integration Strategy

Intel is pursuing a more vertically integrated path by developing its own silicon photonics materials and fabrication processes. Intel’s strategy involves the use of integrated laser sources and high-speed modulators etched directly into the silicon. This reduces the reliance on external components and allows Intel to control the entire signal chain from the processor to the fiber optic cable.

Intel has demonstrated the ability to integrate multiple optical channels on a single chip, which is critical for the high-density interconnects required by AI accelerators. Their roadmap emphasizes the transition from pluggable optics to integrated CPO to lower the Total Cost of Ownership (TCO) for hyperscale data center operators.

Samsung and GlobalFoundries Foundry Approaches

Samsung is integrating CPO capabilities into its broader HBM (High Bandwidth Memory) and logic foundry offerings. By combining optical connectivity with advanced memory stacking, Samsung seeks to solve the “memory wall” problem, where the speed of data movement between memory and the processor becomes the primary bottleneck in AI training.

GlobalFoundries is focusing on the specialized manufacturing of silicon photonic wafers. Their roadmap emphasizes the use of mature process nodes that are optimized for photonics rather than the smallest possible transistor size. This approach prioritizes yield and reliability, providing a cost-effective alternative for companies that do not require the extreme density of leading-edge logic nodes.

Technical Trade-offs in CPO Implementation

The transition to CPO introduces significant engineering challenges that the four foundries are addressing differently. One primary concern is thermal management; because optical components are sensitive to heat, placing them next to a high-wattage AI GPU can cause signal drift or component failure.

Foundries are testing two main architectural paths to solve this:

• Integrated Lasers: Placing the light source directly on the chip, which maximizes efficiency but increases heat sensitivity.
• External Laser Sources (ELS): Keeping the laser in a separate, cooler module and piping the light into the CPO package, which improves reliability and serviceability at the cost of some signal loss.

The adoption of CPO is expected to accelerate as the industry moves toward 1.6T and 3.2T connectivity standards, where traditional electrical interfaces can no longer maintain signal integrity over the required distances on a printed circuit board.