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Unlock the Power of STWPLLSim: Revolutionizing Your Design Experience with STMicroelectronics

September 11, 2024 Catherine Williams - Chief Editor Tech

Optimizing Phase Noise‍ in 9GHz Design with STUW81300

Hello, ‌I’m working ​on ​creating a ‌9GHz ⁣design‍ with excellent ⁣phase noise using the STUW81300. The reference ⁢frequency⁤ is 50MHz, and the PDF is also⁢ 50MHz, with a single-ended configuration.

To design the loop filter, I⁤ utilized STWPLSim v5.3. However, upon comparing the‌ actual measurements with the simulated values, I noticed a discrepancy of 3 to 7 ⁢dB. The settings appear to be ⁣correct, and⁣ I’m seeking advice⁤ on whether this ⁤difference is normal⁤ or if there’s ​an issue with the design.

Simulation Results

  • -81dBm/Hz at 100Hz offset
  • -94dBm/Hz at 1KHz offset
  • -102dBm/Hz​ at 10KHz offset
  • -106dBm/Hz at 100KHz offset
  • -124dBm/Hz ‍at 1MHz offset

Measurement Results

  • -77dBm/Hz at‌ 100Hz offset
  • -88dBm/Hz at 1KHz offset
  • -95dBm/Hz at 10KHz offset
  • -103dBm/Hz at 100KHz​ offset
  • -120dBm/Hz at 1MHz​ offset

I ‌would appreciate any guidance on this matter, as I’m unsure whether the⁣ discrepancy is within normal limits‍ or if there’s a⁢ problem with ⁤the design.

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